Article ID: 000078937 Content Type: Troubleshooting Last Reviewed: 11/15/2011

Simulation Fails for Stratix V Designs Generated Using SOPC Builder

Environment

  • Quartus® II Subscription Edition
  • Ethernet
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT

    Critical Issue

    Description

    Simulation fails when you use the SOPC builder to generate Verilog HDL or VHDL simulation models for designs targeting Stratix V devices.

    This issue affects all Triple-Speed Ethernet designs targeting Stratix V devices.

    Resolution

    No workaround.

    This issue will be fixed in a future version of the Triple Speed Ethernet MegaCore function.

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