Article ID: 000078772 Content Type: Troubleshooting Last Reviewed: 09/27/2011

Some Cyclone III RapidIO Designs Fail Hold Time Requirements in TimeQuest Timing Analyzer

Environment

  • Quartus® II Subscription Edition
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT

    Critical Issue

    Description

    RapidIO x1 variations at data rate 3.125 Gbaud that target a Cyclone III device compile with a critical warning from the TimeQuest timing analyzer indicating that timing requirements are not met and worst-case hold slack is negative.

    Because these variations do not meet timing requirements using the default place and route settings, a design that contains one of these variations does not operate properly.

    Resolution

    Turn on the fitter setting Perform Clocking Topology Analysis During Routing before compiling your RapidIO design.

    This issue is fixed in version 10.1 of the RapidIO MegaCore function.

    Related Products

    This article applies to 2 products

    Cyclone® FPGAs
    Cyclone® III FPGAs