Description
This warning may be seen in the Quartus® II software during fitting when a clock constraint has been assigned in a Synopsys Design Constraints (.sdc) file to a clock control block. The problem occurs because the Fitter reads .sdc file before instantiating clock control blocks. When the .sdc file is read, this node will not be found in the netlist.
To avoid this warning in the Quartus II software, follow one of two solutions.
- Instantiate the clock control block in your design source file code.
- Modify the .sdc file to apply the clock assignment to the source of the clock instead of the clock control block.
For example:
Original assignment
create_clock -name {core_clk_out} -period 8.000 \
[get_nets {*altpcie_hip_pipen1b_inst_PLL|core_clk_out~clkctrl}]Modified assignment
create_clock -name {core_clk_out} -period 8.000 \
[get_nets {*altpcie_hip_pipen1b_inst_PLL|core_clk_out}]