Article ID: 000078652 Content Type: Troubleshooting Last Reviewed: 05/23/2023

Why does the EDCRC soft IP gate-level simulation netlist file for my Arria® V GX ES design not compile successfully in the ModelSim simulator?

Environment

  • Quartus® II Subscription Edition
  • Simulation
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    During compilation in the Quartus® II software version 11.1 SP2, EDCRC soft IP is inserted for Arria® V GX ES devices. This soft IP contains an internal oscillator that does not have a simulation model. As a result, VHDL output (.vho) and Verilog HDL output (.vo) gate-level simulation netlist files may not compile successfully in the ModelSim software. You might see the following errors:

    Error: ModelSim Error: # ** Error: <design>.vho(<line number>): (vcom-1035) Formal port "ntrst" has OPEN or no actual associated with it.
    Error: ModelSim Error: # ** Error: <design>.vho(<line number>): (vcom-1035) Formal port "tdoutap" has OPEN or no actual associated with it.
    Error: ModelSim Error: # ** Error: <design>.vho(<line number>): (vcom-1141) Identifier "arriav_oscillator" does not identify a component declaration.

    Resolution

    A patch is available to work around this limitation in the Quartus II software version 11.1 SP2. Download and install Patch 2.12 from the appropriate link below. After installing the patch, you can use a variable in the quartus.ini file in your project directory to control compilation. To generate a gate-level simulation netlist, create or edit a quartus.ini file in your project directory and add the following line:

    sgn_add_av_es_soft_ip=off

    This variable disables the auto-insertion of EDCRC soft IP and allows the gate-level simulation netlist file to compile successfully in the ModelSim software. However, programming files will not be generated. To generate programming files, you must remove the variable from the quartus.ini file. Download the following patch:

    Related Products

    This article applies to 1 products

    Arria® V GX FPGA