Cadence NC-Sim software error: ncelab: *F,GENPAR: VHDL generic ALTERA_MULT_ADD.ACCUM_DIRECTION (./cplxmult.vhd: line 65, position 16) and verilog parameter being overridden altera_mult_add.extra_latency (/tools/acdskit/11.0/140/linux64/quartus/eda/sim_lib

In the Cadence NC-Sim software, if you attempt to perform, using altera_lnsim.sv, RTL simulation of a VHDL design that contains an ALTMULT_ADD megafunction, the NC-Sim software issues the following error:

Cadence NC-Sim software error: ncelab:*F,GENPAR: VHDL generic ALTERA_MULT_ADD.ACCUM_DIRECTION (./cplxmult.vhd:line 65, position 16) and verilog parameter being overridden altera_mult_add.extra_latency (/tools/acdskit/11.0/140/linux64/quartus/eda/sim_lib/altera_lnsim.sv:line 3631, position 23) are not type compatible.

To prevent the error, use the -namemap_mixgen option with the ncelab command.