Why do I see OpenCore warnings for my Qsys based design containing the Altera Triple Speed Ethernet IP core?

Due to a problem in the Quartus® II software versions 11.1 and 12.1, QSYS Systems containing the Altera Triple Speed Ethernet MAC IP core will compile in OpenCore mode, and programming files may not be generated.

The following warnings may be seen during Analysis and Synthesis:
Warning (12189): OpenCore Simulation-Only Evaluation feature is turned on for all cores in the design
Warning (12191): Some cores in this design do not support the OpenCore Plus Hardware Evaluation feature
Warning (12192): ""Triple Speed Ethernet" (6AF7_0104)" does not support the OpenCore Plus Hardware Evaluation feature

To workaround this issue follow the steps below: 

1. Open the .qip file generated for the Qsys system in a text editor <qsys system name>/synthesis/<qsys system name>.qip
2. Delete the Assignments in the .qip file for the following files:
   altera_tse_ptp_1588_rx_top.ocp
altera_tse_ptp_1588_tx_top.ocp
altera_tse_ptp_inserter.v
altera_tse_avst_to_gmii_if.v
altera_tse_gmii_to_avst_if.v
altera_tse_ptp_1588_crc.v
altera_tse_ptp_1588_rx_top.v
altera_tse_ptp_1588_tx_top.v
altera_tse_timestamp_req_ctrl.v
altera_tse_tsu.v
3. Save the updated .qip file
4. Re-compile your Quartus II project

Note: The workaround must be repeated if the Qsys system is re-generated

This problem will be fixed in a future version of the Quartus II software.