Timing constraints in Synopsys Design Constraint (SDC) format can be embedded in VHDL or Verilog HDL design files when using Quartus® II synthesis.
Use the altera_attribute keyword in your HDL file and the SDC_STATEMENT option to apply a timing constraint. Only one altera_attribute is allowed per VHDL entity or Verilog HDL module.
To apply multiple constraints, combine all options or assignments into one line, separating each with a semicolon (;).
Below is an example of applying multiple false-path timing constraints using the altera_attribute keyword and the SDC_STATEMENT option in Verilog-2001 HDL format. For other HDL language formats, refer to Using altera_attribute to Set Quartus II Logic Options in the Quartus® II Integrated Synthesis (PDF) chapter of the Quartus® II Handbook.
(* altera_attribute = {"-name SDC_STATEMENT \"set_false_path -from [get_registers *sv_xcvr_pipe_native*] -to [get_registers *altpcie_rs_serdes|*]\";-name SDC_STATEMENT \"set_false_path -to [get_registers *altpcie_rs_serdes|fifo_err_sync_r\[0\]]\";-name SDC_STATEMENT \"set_false_path -to [get_registers *altpcie_rs_serdes|busy_altgxb_reconfig*]\""} *)