Article ID: 000078292 Content Type: Error Messages Last Reviewed: 04/07/2014

Error: Standard RX/TX PCS Parameter 'hd_pcs8g_digi_rx/tx_byte_deserializer' is set to an illegal value of 'en_bds/bs_by_2'. This mode is not supported with device speed grade of '8_H6', PMA WIDTH of 'twenty_bit' on atom.

Environment

  • Cyclone® V SX SoC FPGA
  • Cyclone® V GX FPGA
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Description

You may see the following Quartus® II software fitter error when using the transceiver PHY instance and the “enable Byte Serializer/Deserializer with 16- and 20-Bit PMA-PCS Widths” option is selected on Cyclone® V GX/SX, -6 transceiver and -8 device speed grade devices.

Error: Standard RX PCS Parameter 'hd_pcs8g_digi_rx_byte_deserializer' is set to an illegal value of 'en_bds_by_2'. This mode is not supported with device speed grade of '8_H6', PMA WIDTH of 'twenty_bit' on atom '<variation name>|av_hssi_8g_rx_pcs_rbc:inst_av_hssi_8g_rx_pcs|wys'.

Error: Standard TX PCS Parameter 'hd_pcs8g_digi_tx_byte_serializer' is set to an illegal value of 'en_bs_by_2'. This mode is not supported with device speed grade of '8_H6', PMA WIDTH of 'twenty_bit' on atom '<variation name>|av_hssi_8g_tx_pcs_rbc:inst_av_hssi_8g_tx_pcs|wys '.

This combination of -6 transceiver and -8 device speed grades are not supported when the “enable Byte Serializer/Deserializer with 16- and 20-Bit PMA-PCS Widths” option is selected.

Resolution

To work around this problem, you can reduce your transceiver PHY parallel width.

This information is scheduled to be added to a future version of the Cyclone V Device Handbook.

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