Article ID: 000078155 Content Type: Product Information & Documentation Last Reviewed: 11/08/2022

How do I instantiate a differential input or output buffer in my design?

Environment

BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description

You can instantiate a differential input or output buffer in your design using the ALTIOBUF Intel® FPGA IP core available in the Intel® Quartus® Prime Software. 

Resolution

The ALTIOBUF Intel® FPGA IP core allows you to specify your input or output pin as a differential receiver or transmitter and then you need to port both the positive and negative signals to I/O pins.  This Intel FPGA IP core is supported beginning with the Stratix® III and Cyclone® III device families.

For Stratix® II, Cyclone® II, Arria® GX, and previous device families, you cannot instantiate a differential buffer in your design. Instead, use the positive leg of the differential pair in your design, and locate that pin in the Assignment Editor. Give that pin an I/O standard assignment with a value of "LVDS" or the differential I/O standard you wish to use.  Refer to the device handbook for a complete listing of the supported I/O standards. The negative leg will automatically be assigned to the corresponding complimentary pin by the fitter when you compile your design. This method is supported for all device families that support differential I/O standards such as LVDS.

For more information on the ALTIOBUF Intel FPGA IP core, refer to the ALTIOBUF IP Core User Guide (PDF).

Related Products

This article applies to 7 products

Arria® II FPGAs
Arria® V FPGAs and SoC FPGAs
Cyclone® IV FPGAs
Cyclone® V FPGAs and SoC FPGAs
Intel® Cyclone® 10 LP FPGA
Stratix® IV FPGAs
Stratix® V FPGAs