Article ID: 000078117 Content Type: Product Information & Documentation Last Reviewed: 03/17/2023

How do DQ grouping pin assignments affect On-Chip Termination (OCT) block usage in Stratix® V devices?



In Stratix® V devices, I/O pins are grouped into groups of x4, and all I/O pins within a single group can only be driven by one OCT block. When assigning pin location to DQS/DQ pins, pins which are assigned to the same x4 group should share the same OCT calibration block, or do not use OCT if this requirement cannot be met.


If you do not meet this requirement, you will see the following fitter error:


Error (175020): Illegal constraint of pin <pin name> to the region <region value> to <region value>: no valid locations in region


Error (175005): Could not find a location with: OCT_CAL_BLOCK_ID of <value>


Error (171000): Can’t fit design in device.


In the Pin Planner, right-click on the pin diagram. Select “Show DQ/DQS Pins” and then “In x4 Mode”. I/O blocks are differentiated with colors. I/O pins belonging to the same I/O block share the same color. Ensure that the I/O pins that are assigned to the same color share the same OCT calibration block, or do not use OCT.


Related Products

This article applies to 4 products

Stratix® V E FPGA
Stratix® V GS FPGA
Stratix® V GT FPGA
Stratix® V GX FPGA



All postings and use of the content on this site are subject to Terms of Use.