Verilog HDL syntax error: syntax error near end of file?

Description The Quartus^® II software versions 2.1 and above Help indicates some possible causes of this syntax error. This error can also occur in the Quartus II software if you use a /* translate_off */ command with a // translate_on command.

In Verilog HDL, you can indicate comments using // or /* */ . In the Quartus II software version 2.1, if you use the syntax /* synthesis translate_off */ , you must also use /* synthesis translate_on */ not // synthesis translate_on . This restriction was removed in the Quartus II software version 3.0. The Quartus II software supports the following different translate compiler directives:

Verilog HDL:



// synthesis translate_off   // synthesis translate_on 



or



/* synthesis translate_off */ /* synthesis translate_on */



VHDL:



-- synthesis translate_off -- synthesis translate_on

In addition to the synthesis keyword as shown above, the following keywords are supported in both Verilog HDL and VHDL for compatibility with other synthesis tools:

pragma       

synopsys     

exemplar

NOTE: The Quartus II software versions 2.0 and below do not support compiler directives. You will see different behavior in the Quartus II software if designs compiled in earlier versions of the software included these directives. You may need to change your code now that the options are honored by the software since previous versions of the Quartus II Compiler treated the options as just comments.