Article ID: 000077941 Content Type: Troubleshooting Last Reviewed: 05/18/2013

Stratix V Hard IP for PCI Express IP Core Gen3 x8 app_rstn Timing Issue

Environment

    Quartus® II Subscription Edition
BUILT IN - ARTICLE INTRO SECOND COMPONENT

Critical Issue

Description

The Stratix V Hard IP for PCI Express IP Core Gen3 x8 example design has timing failures related to the app_rstn signal.

Resolution

This issue is fixed in release 13.0 of the Quartus II software.

Related Products

This article applies to 1 products

Stratix® V FPGAs

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