Due to a problem in the Quartus® II software version 11.1 and later on Linux, memory initialisation files (.hex .mif) specified for Altera memory block components (VHDL / Verilog) may not be found during Analysis and Synthesis if the source files are added as project files using full paths, and are located under automounted directories.
For example, from the Quarrtus II settings file (.qsf) for a project:
set_global_assignment -name <VERILOG_FILE / VHDL_FILE> /net/serverMyServer/myProject/source/ram1.<v/vhd>
To workaround this issue HDL source files located on paths from /net should be added to your Quartus II project using relative paths. Linux soft links can be used to achieve this by following the steps shown below:
For example, where the original file path as defined in the Quartus Settings File for your project (.qsf) is:set_global_assignment -name <VERILOG_FILE / VHDL_FILE > /net/serverMyServer/myProject/source/ram1.<v/vhd>
1. Create a new directory within your Quartus II project directory to contain links to your source files:
mkdir source
2. Move into the new directory:
cd source
3. Create softlinks from your source files:
ln -s /net/serverMyServer/myProject/source/ram1.<v/vhd> .
4. Update the file path in the Quartus Settings File (.qsf) for your project :
set_global_assignment -name <VERILOG_FILE / VHDL_FILE > source/ram1.<v/vhd>
This problem is fixed beginning with the Quartus II software version 12.0 SP1.