Article ID: 000077864 Content Type: Troubleshooting Last Reviewed: 02/08/2013

Mismatched VHDL generic and local parameter types in NC-Sim for Stratix V fractional PLL simulation models

Environment

    Quartus® II Subscription Edition
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Critical Issue

Description

If you use Cadence Incisive version 11.10.017 to simulate a Stratix V design that includes a fractional phase-locked loop (PLL), and if a VHDL generic parameter and a local parameter have the same name regardless of case, NC-Sim might incorrectly match the two parameters.

For example, NC-Sim matches a generic parameter named pll_lock_fltr_test and a localparam named PLL_LOCL_FLTR_TEST.

Resolution

Upgrade to Incisive version 11.10.060 or later.

Related Products

This article applies to 1 products

Stratix® V FPGAs

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