Article ID: 000077856 Content Type: Troubleshooting Last Reviewed: 08/21/2023

How do I generate Configuration via Protocol (CvP) programming files for Arria® V or Cyclone® V designs?

Environment

    Quartus® II Subscription Edition
    Arria® V Hard IP for PCI Express Intel® FPGA IP
BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description

To generate CvP programming files for Arria® V or Cyclone® V CvP designs with Quartus® II software version 13.1 and earlier, follow the workaround/fix steps below:

 

 

 

Resolution

Ensure that you have a CvP fixed die revision capable device.  

To do this, refer to the Configuration via Protocol section of the Device Errata Sheet for the required die codes.

The workaround requires the following steps:

a) Add/Create the following. INI variables in a quartus.ini file in your Quartus® project directory ( <Working_Directory>/ ) to enable CvP programming file generation

PGMIO_ENABLE_CVP=ON
PGMIO_ENABLE_AUTONOMOUS_HIP_MODE=ON

PGMIO_CREATE_CVP_FILES=ON

PGMIO_DISABLE_AV_CV_AUTONOMOUS=OFF
ASM_FORCE_ENABLE_AUTONOMOUS_PCIE_HIP=ON

 

b) Optionally add the following QSF settings if you want to utilize the following pin feature:

•  Enable the CvP CONFDONE pin

set_global_assignment -name ENABLE_CVP_CONFDONE ON

•  Set the CvP CONFDONE pin type

set_global_assignment -name CVP_CONFDONE_OPEN_DRAIN ON

Related Products

This article applies to 6 products

Cyclone® V FPGAs and SoC FPGAs
Arria® V GX FPGA
Arria® V FPGAs and SoC FPGAs
Arria® V GT FPGA
Cyclone® V GX FPGA
Cyclone® V GT FPGA

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