Article ID: 000077698 Content Type: Troubleshooting Last Reviewed: 09/26/2011

Unstable Designs with LVDS in Hardware

Environment

  • Quartus® II Subscription Edition
  • Ethernet
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT

    Critical Issue

    Description

    You may get unstable results when running designs that contain LVDS transceiver blocks in hardware. This is caused by the constraints provided with the MegaCore function.

    This issue affects all configurations that contain LVDS transceiver blocks.

    Resolution

    Edit the constraint file, <project directory>/variation name>_constraint.sdc., and replace lines 410 through 417 with the following lines:

    set_clock_groups -asynchronous -group {altera_tse_mac_rx_clk_0} -group {altera_tse_mac_tx_clk_0} -group {altera_tse_rx_afull_clk} -group {altera_tse_sys_clk} -group {altera_tse_ref_clk \ altera_tse_multi_mac_pcs_pma_inst|the_altera_tse_pma_lvds_rx_0|altlvds_rx_component|auto_generated|rx[0]|clk0 \ altera_tse_multi_mac_pcs_pma_inst|the_altera_tse_pma_lvds_rx_0|altlvds_rx_component|auto_generated|pll|clk[0]}

    This issue will be fixed in a future version of the Triple-Speed Ethernet MegaCore function.

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