It is not recommended to share the
refclk between the PCIe® Hard IP core and the external memory interface IP core, which includes all UniPHY and ALTMEMPHY-based controllers. The PCIe interface and the external memory interface need their PLL
refclk directly from different dedicated clock input pins.
In order for the memory controller to use the same clock as the PCIe Hard IP core, it would need to cascade the
coreclkout signal of the PCIe Hard IP core to the refclk input of the memory IP core. This is not recommended because the additional jitter caused by the global clock routing resource will affect the external memory interface performance.