Starting in Quartus® II software version 10.1 SP1, there were changes to the implementation of the PCI Express® IP when using Qsys and SOPC Builder. The changes implemented connections to this and other signals / ports, within the IP, relieving the customer from needing to address them. This is the reason these signals / ports are not brought out to the top-level connection list of the IP in the system tools, Qsys and SOPC Builder.
Unfortunately, the underlying implementation results in warning message. These warning messages can safely be ignored.
Other signals / ports that may produce the same warning message and can safely be ignored:
pcie_internal_hip.rc_rx_digitalreset
pcie_internal_hip.tx_deemph_<x> where x = 1 to the number of lanes supported
pcie_internal_hip.tx_margin_<x> where x = 1 to the number of lanes supported
pipe_interface_internal.pll_powerdown_pcs
pipe_interface_internal.rateswitch_pcs
pipe_interface_internal.rateswitchbaseclock_pcs
refclk_conduit.conduit_out_<2:9>
This will be fixed in a future release of the Quartus II software.