Article ID: 000077461 Content Type: Troubleshooting Last Reviewed: 06/01/2021

Why might I see incorrect clock frequency in the khz_rx (0x341) and khz_tx (0x342) registers of E-Tile Hard IP for Ethernet Intel® FPGA IP ?

Environment

  • Intel® Stratix® 10 MX FPGA
  • Intel® Stratix® 10 TX FPGA
  • Intel® Stratix® 10 DX FPGA
  • Intel® Agilex™ I-Series FPGAs and SoC FPGAs
  • Intel® Quartus® Prime Pro Edition
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    Critical Issue

    Description

    You might see incorrect frequency in the khz_rx (0x341) and khz_tx (0x342) registers of E-Tile Hard IP for Ethernet Intel® FPGA IP if the i_reconfig_clk frequency is not 100 MHz.

    Because the frequency value is measured on the assumption that the i_reconfig_clk frequency is 100 MHz.

    Resolution

    If the i_reconfig_clk frequency is not 100 MHz, the khz_rx (0x341) and khz_tx (0x342) register values are calculated with the equation below, respectively. 

    • khz_tx (0x341) : Recovered clock frequency /10* [100 MHz / i_reconfig_clk (MHz) ], in KHz
    • khz_tx (0x342) : TX clock frequency /10* [100 MHz / i_reconfig_clk (MHz) ], in KHz

    The description problem is scheduled to be fixed in a future release of the UG-20160.

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