Article ID: 000077428 Content Type: Troubleshooting Last Reviewed: 04/17/2023

Does the ATX PLL to fPLL spacing rule on Intel® Stratix®10 L-Tile and H-Tile devices apply to fPLLs in Core mode?

Environment

    Intel® Quartus® Prime Pro Edition
    L-Tile H-Tile fPLL Intel® Stratix® 10 FPGA IP
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Description

Yes. The ATX PLL to fPLL spacing rule on Intel® Stratix® 10 L-Tile and H-Tile devices applies to fPLLs in Core and transceiver modes.

 

 

Resolution

If you violate this rule with your fPLL in either mode, the Intel Quartus® Prime Software will issue a critical warning.

Related Products

This article applies to 1 products

Intel® Stratix® 10 FPGAs and SoC FPGAs

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