Article ID: 000077423 Content Type: Troubleshooting Last Reviewed: 10/16/2018

Why does the Intel® Stratix® 10 SoC FPGA Hard Processor System hang after a warm reset or watchdog warm reset?

Environment

  • Intel® Quartus® Prime Pro Edition
  • Intel® SoC FPGA Embedded Development Suite (SoC EDS) Pro Edition
  • Hard Processor System Intel® Stratix® 10 FPGA IP
    • BUILT IN - ARTICLE INTRO SECOND COMPONENT

    Critical Issue

    Description

    The Intel® Stratix® 10 SoC FPGA Secure Device Manager(SDM) is not able to bring the HPS out of warm or watchdog reset after a reconfiguration. Additionally if a warm reset or watchdog warm reset has occurred, any subsequent attempt to reconfigure the device may fail.

     

    Resolution

    Please use the Intel Quartus™ Prime Pro software version 18.1 build 222 with patch 0.01, available at:

    quartus-18.1-0.01dp1-linux.run

    quartus-18.1-0.01dp1-windows.exe

     

    Related Products

    This article applies to 1 products

    Intel® Stratix® 10 SX SoC FPGA

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