Article ID: 000077400 Content Type: Troubleshooting Last Reviewed: 04/17/2023

Why don’t my Intel® Stratix® 10 device E-Tile Native PHY IP TX equalization settings match what is read from the PMA attribute register, or what is displayed in the Intel Quartus® software Transceiver Toolkit.


  • Intel® Quartus® Prime Pro Edition
  • Stratix® 10 E-Tile Transceiver Native PHY

    Due to a problem in Intel® Quartus® Prime Software version 19.2 and earlier, your user-defined Stratix 10 device E-Tile Native PHY IP TX equalization settings may not be correctly incorporated into the <project_name>.sof programming file.

    The following conditions may cause TX equalization settings not to be written to the <project_name>.sof file

    • Unsupported Attenuation, Pre-tap 1, Pre-tap 2, Pre-tap 3, or Post-tap 1 equalization settings.
    • A non-zero ATTEN value.

    The equalization settings read from the PMA attribute register or displayed in the Intel Quartus Prime Transceiver Toolkit represent the actual equalization settings in the PHY.



    To work around this problem, refer to the E-Tile Transceiver PHY User Guide and only enter supported TX equalization settings into the E-Tile Native PHY IP.

    If you want to use non-zero TX equalization settings, write to the PHY using the PMA attribute codes after the FPGA configuration.

    This problem was fixed in Intel® Quartus® software version 19.3

    Related Products

    This article applies to 2 products

    Intel® Stratix® 10 TX FPGA
    Intel® Stratix® 10 MX FPGA