Article ID: 000077400 Content Type: Troubleshooting Last Reviewed: 08/12/2019

Why don’t my Intel® Stratix® 10 device E-Tile Native PHY IP TX equalization settings match what is read from the PMA attribute register, or what is displayed in the Intel Quartus® Transceiver Toolkit.


  • Intel® Quartus® Prime Pro Edition
  • Stratix® 10 E-Tile Transceiver Native PHY

    Due to a problem in Quartus Prime software version 19.2 and earlier, your user-defined Stratix 10 device E-Tile Native PHY IP TX equalization settings may not be correctly incorporated into the <project_name>.sof programming file.

    The following conditions may cause TX equalization settings to not be written to the <project_name>.sof file

    • Unsupported Attenuation, Pre-tap 1, Pre-tap 2, Pre-tap 3, or Post-tap 1 equalization settings.
    • A non-zero ATTEN value.

    The equalization settings read from the PMA attribute register, or displayed in the Intel Quartus Prime Transceiver Toolkit represent the actual equalization settings in the PHY.



    To work around this problem, you can refer to the E-Tile Transceiver PHY User Guide and only enter supported TX equalization settings into the E-Tile Native PHY IP.

    If you want to use non-zero TX equalization settings, you can write to the PHY using the PMA attribute codes after FPGA configuration.

    This problem will be fixed in a future version of the Intel Quartus Prime software.

    Related Products

    This article applies to 2 products

    Intel® Stratix® 10 TX FPGA
    Intel® Stratix® 10 MX FPGA



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