Article ID: 000077368 Content Type: Troubleshooting Last Reviewed: 07/07/2020

Why does the fPLL of the Intel® Stratix® 10 L- and H-tile device in fractional mode lose lock after calibration ?


  • Intel® Quartus® Prime Pro Edition

    When the fPLL of an Intel® Stratix® 10 L- and H-tile device is configured in fractional mode and its VCO frequency range is less than 7 GHz, fPLL registers may not be set to the calibrated value after fPLL power-up calibration or user-recalibration.


    To work around the problem, reset fPLLs that lose lock after calibration by writing the following sequence to soft control registers through the fPLL Avalon Memory Mapped dynamic reconfiguration interface.

    1. Set register 0x4E0[1] to 1
    2. Set register 0x4E0[0] to 1
    3. Set register 0x4E0[0] to 0
    4. Set register 0x4E0[1] to 0 

    You should tick the Enable Dynamic Reconfiguration, Enable Native PHY Debug Master Endpoint, and Enable Control and Status Registers options in the Intel Stratix 10 L- and H-tile device fPLL IP in order to write to the soft control registers above.

    Related Products

    This article applies to 4 products

    Intel® Stratix® 10 MX FPGA
    Intel® Stratix® 10 TX FPGA
    Intel® Stratix® 10 SX SoC FPGA
    Intel® Stratix® 10 GX FPGA



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