Article ID: 000076982 Content Type: Troubleshooting Last Reviewed: 01/01/2015

What is the loopback mode supported by Altera PCIe Hard IP core?



PCIe® Hard IP (HIP) core does not support Loopback Master, but it supports Loopback Slave via PCIe Reverse Parallel Loopback configuration as indicated in device Transceiver Architecture chapter.

The following list describes the loopback sequence:
1. The PCIe HIP core enters Loopback state when RC asserts loopback bit (bit2 of symbol 5) in TS1/TS2 during Configuration.LinkWidth.Start state.  Both EP and RC must follow the rules as defined in PCI Express Base specification.
2. After successfully entering Loopback state, the core automatically asserts tx_detectrxloopback=1 and txelecidle=0 as required by PIPE interface spec. This will instruct the Altera transceiver to route the data after the Rate Match FIFO in Receiver Channel PCS to the associated Transmitter Channel. The receive data will pass through the CDR, deserializer, 8b/10b decoder, Word Aligner, and Rate Match FIFO before looping back to the transmit side. The transmit data will pass through the Rate Match FIFO, 8b/10b encoder and serializer before being transmitted out.
3. The RC transmits 8b/10b encoded patterns to the EP receiver during loopback mode as required by PCI Express Base spec. It also needs to send SKIP OS to make sure the Rate Match FIFO does not overflow or underflow. Similarly SKIP OS's will be inserted by the Rate Match FIFO in the EP transmit direction as required. Therefore, the EP transmit monitor must take this into account when comparing the looped back transmit data with the original  receive data.  The loopback pattern cannot be PRBS data because it is not 8b/10b encoded PCIe data.
4. To guarantee that good data is received properly, AC coupling is needed between RC transmit pins and the EP receive pins. As per the PCIe CEM (Plug in board) specification, the AC Coupling capacitors are always on the board with the transmit device pins. If a tester is hooked up to our card that is plugged into the PCI-SIG Compliance Base Board (CBB) via coax cables and the CBB does not have AC Coupling capacitors, physical DC blocks must be added in line with the cables to provide the same effect. So either AC Coupling capacitors or physical DC blocks are required between each RC transmit and the EP receive pin.
5. The system reference clock on the RC and EP must operate within /-300ppm according to PCIe spec.
This is why the PCIe spec specifies that the loopback should pass through the Rate Match FIFO which can insert or delete SKIP OS's as needed to handle this range.

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This article applies to 3 products

Stratix® IV GT FPGA
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