Description
The Quartus® II software generates this warning during Analysis & Synthesis if a module output that can be tri-stated is assigned as a virtual pin. The internal logic in Altera® devices does not support tri-state operation; you may want to consider using a multiplexer structure. If a module output has tri-state capability, the Quartus II software inserts an I/O buffer to account for the tri-state enable logic. Therefore, the output cannot be assigned as a virtual pin.
To avoid this warning, do not use tri-state logic except for signals that connect directly to device I/O.