Critical Issue
Description
If the Intel Agilex® 3 FPGA DDR4 intellectual property (IP) simulation design example is generated using the Intel® Quartus® Prime Pro Edition Software version 19.3 or later, you might see the following errors when performing register transfer level (RTL) simulation using the Aldec Riviera-PRO tool.
Error: Simulation initialization failed.
Fatal Error: run.do : (4, 1): Script execution terminated due to error(s).
Resolution
This problem is fixed starting with the Intel® Quartus® Prime Pro Edition Software version 21.3.