Critical Issue
Description
The top level Verilog HDL module for the PCI Express IP core
includes the derr_cor_ext_rcv1 signal; however, this
signal is not required or functional for Stratix V devices.
This issue affects all configurations of the Stratix V Hard IP for PCI Express.
Resolution
After generating your Stratix V Hard IP for PCI Express, remove derr_cor_ext_rcv1 from
the <pcie_variant>.v.
This issue is fixed in version 11.0 SP1 of the Stratix V Hard IP for PCI Express.