Article ID: 000076874 Content Type: Troubleshooting Last Reviewed: 10/02/2019

Why doesn't the Intel® Stratix® 10 Avalon-MM Interface PCIe* HIP reflect MSI-X parameters in the IP Catalog ?

Environment

  • Intel® Quartus® Prime Pro Edition
  • Avalon-MM Intel® Stratix® 10 Hard IP for PCI Express
    • BUILT IN - ARTICLE INTRO SECOND COMPONENT

    Critical Issue

    Description

    Due to a problem in the Intel® Quartus® Prime Pro Edition software version 19.2 or earlier, the MSI-X parameters below shown in the GUI do not match the params in the generated RTL.

        - Table offset
        - Pending bit array (PBA) offset

     

    Resolution

    To work around this problem, modify the parameters below in the "altera_pcie_s10_hip_avmm_bridge.v".

    parameter  [28:0]           pf0_pci_msix_pba_offset                                                         =   29'h2000                                    ,
    parameter  [28:0]           pf0_pci_msix_table_offset                                                       =   29'h3000

    This problem is fixed in the Intel® Quartus® Prime Pro software version 19.3 and beyond.

    Related Products

    This article applies to 4 products

    Intel® Stratix® 10 SX SoC FPGA
    Intel® Stratix® 10 GX FPGA
    Intel® Stratix® 10 MX FPGA
    Intel® Stratix® 10 TX FPGA

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