Article ID: 000076830 Content Type: Troubleshooting Last Reviewed: 05/05/2021

Why does the 25G Ethernet Intel® FPGA IP fail to achieve 100% throughput?

Environment

  • Intel® Arria® 10 FPGAs and SoC FPGAs
  • Intel® Stratix® 10 FPGAs and SoC FPGAs
  • Intel® Quartus® Prime Pro Edition
  • Intel® Quartus® Prime Standard Edition
  • 25G Ethernet Intel® FPGA IP
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    Description

    Due to problem in the 25G Ethernet Intel® FPGA IP core, for Intel® Quartus® Prime<Pro/Standard> version 20.2 and earlier, you may see the IP fail to achieve 100% throughput.

    This is because the IP does not compensate for the data rate loss due to RSFEC Alignment Marker Insertion on the TX data path. The 25G Ethernet Intel® FPGA IP Core is not adhering to section 108.5.2.2 "rate compensation for codeword markers in the transmit direction" of the IEEE 802.3 spec. As a result, the IP is unable to achieve throughput higher than 99.995%.

    Resolution

    No workaround to this problem exists.

    This problem is scheduled to be fixed in future release of the Intel® Quartus® Prime <Pro/Standard> Edition software.

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