Is there a known problem with the master_reset output of the JTAG to Avalon Master Bridge component when using Intel® Stratix® 10 FPGA or Intel Agilex® 7 devices?

Yes, due to a known problem in the Intel® Quartus® Prime Pro Edition Software version 20.4 and earlier, the master_reset output of the JTAG to Avalon Master Bridge component may be unstable and create spurious reset assertions when used in Intel® Stratix® 10 FPGA or Intel Agilex® 7 devices. 

This is because the JTAG logic that produces this asynchronous reset output is not reset after configuration and since the initial state of the register is unknown, the behavior of this reset output is unpredictable after device configuration.

Do not use the master_reset output of the JTAG to Avalon Master Bridge IP as a reset source to any logic when using the Intel® Stratix® 10 FPGA or the Intel Agilex® 7 devices.