When targeting the Intel® Arria® 10, Intel® Cyclone® 10 GX, or Intel® Stratix® 10, devices, the JESD204B IP design example components (IOPLL/Core PLL and ATX PLL) share the same reference clock frequency with the CDR reference clock.
You might see errors in the Intel® Quartus® Prime Pro Edition Software v17.0 or later during JESD204B IP design example generation or compilation. This is due to the selected reference clock frequency not being valid for other design example components.
The following are examples of error messages that might be seen:
Error: altjesd_ed_qsys_RX_TX_xcvr_atx_pll_0.xcvr_atx_pll_0: "N counter" (atx_pll_ref_clk_div) 0 is out of range: 1-2, 4, 8
Error: altjesd_ed_qsys_RX_TX_xcvr_atx_pll_0.xcvr_atx_pll_0: "PLL auto mode reference clock frequency (Integer)" (set_auto_reference_clock_frequency) 34.5 is out of range
Error: qsys-generate failed with exit code 3
Error: altjesd_ed_qsys_RX_TX_core_pll.core_pll: Failed to compute output counter 0 frequency dropdown values: Failed to retrieve freq list.
Error: altjesd_ed_qsys_RX_TX_core_pll.core_pll: Reference clock frequency 780.878049 is out of legal range (10.0:750.0)
Error: altjesd_ed_qsys_RX_TX_core_pll.core_pll: "Reference Clock Frequency" (gui_reference_clock_frequency) 780.878049 is out of range: 10.0-750.0
To work around this problem, choose another reference clock frequency from the PLL/CDR Reference Clock Frequency drop-down list in the JESD204B IP parameter editor, and regenerate the design example.