Article ID: 000076634 Content Type: Troubleshooting Last Reviewed: 07/24/2017

Why Low Latency Ethernet 10G MAC 10M/100M/1G/10G Example Design may fail timing on multiple channels?

Environment

    Intel® Quartus® Prime Pro Edition
    Low Latency Ethernet 10G MAC Intel® FPGA IP
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Description

The following variants of Intel® Low Latency Ethernet 10G MAC example design may fail timing when number of channel more than or equal to 7.
 1. 10M/100M/1G/10G Ethernet
 2. 10M/100M/1G/10G Ethernet with 1588
 3. 1G/10G Ethernet
 4. 1G/10G Ethernet with 1588

Resolution

This issue has been fixed in Quartus® Prime software versions 17.0 and onwards.

Related Products

This article applies to 4 products

Intel® Arria® 10 GX FPGA
Arria® V FPGAs and SoC FPGAs
Stratix® V FPGAs
Intel® Stratix® 10 FPGAs and SoC FPGAs

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