Article ID: 000076589 Content Type: Troubleshooting Last Reviewed: 11/08/2017

Why does the Arria V and Stratix V HDMI design example cause no display or image distortion on HDMI sink ?

Environment

  • Intel® Quartus® Prime Pro Edition
  • HDMI Intel® FPGA IP
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT

    Critical Issue

    Description

    When using Arria®V and Stratix®V HDMI IP core design example, switching between different color space using certain HDMI source might cause no display or image distortion on the HDMI sink.

    The root cause is that there is a problem in the read request from the auxiliary bypass FIFO. This caused missing end-of-packet in the last auxiliary packet.

    The problem occurs when the last auxiliary packet which missing end-of-packet involves auxiliary video information (AVI) infoFrame, which contains the color space information required by the HDMI sink.

    Resolution

    This problem has been fixed in Quartus® Prime Standard Edition version 17.0 Update 1.

    Related Products

    This article applies to 2 products

    Stratix® V FPGAs
    Arria® V FPGAs and SoC FPGAs