Article ID: 000076584 Content Type: Troubleshooting Last Reviewed: 10/07/2020

Why does the E-Tile Hard IP for Ethernet fail to achieve RX PCS alignment and successfully link up when dynamically reconfigured from 100GbE MAC PCS with RS-REC variant to 100GbE MAC PCS without RS-FEC?

Environment

  • Intel® Agilex™ F-Series FPGAs and SoC FPGAs
  • Intel® Stratix® 10 FPGAs and SoC FPGAs
  • Intel® Quartus® Prime Pro Edition
  • Transceiver PHY Reset Controller Intel® FPGA IP
  • Ethernet
  • Stratix® 10 20 Transceiver PHY Reset Controller
  • Transceiver Reconfiguration Controller Intel® FPGA IP
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    Critical Issue

    Description

    Due to a mistake in the E-Tile Hard IP User Guide, a Reset Controller register required when switching from 100G MAC PCS with RS-FEC to 100G MAC PCS mode is not documented.


    The E-Tile RS-FEC includes a port called rsfec_signal_ok. When performing dynamic reconfiguration from one mode to another the reset controller waits for this signal to assert as part of the reset sequence. However, in the non RS-FEC mode, this signal will not assert, this results in the channel getting stuck in reset when switching from 100G RS-FEC mode to non RS-FEC mode.

    Bit[5] of the undocumented reset controller register at address 0x313 instructs the reset controller to ignore the rsfec_signal_ok port.

    Resolution

    This undocumented E-Tile reset controller register is correctly used in the E-Tile 100G Ethernet Dynamic Reconfiguration Design Example.

    • When switching from 100G MAC PCS with RS-FEC to 100G MAC PCS non RS-FEC mode set Bit[5] of register 0x313
    • When switching from 100G MAC PCS non RS-FEC to 100G MAC PCS with RS-FEC clear Bit[5] of register 0x313

    This missing information has been added to version will be added to release UG-20160|2020.12.14 of the E-Tile Hard IP for Ethernet user guide.

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