Article ID: 000076492 Content Type: Troubleshooting Last Reviewed: 07/08/2020

Why does the JESD204C Intel® FPGA IP in base only mode generated in the Intel® Quartus® Prime Pro Edition version 19.4 require regeneration in Intel® Quartus® Prime Pro Edition version 20.1 and above?

Environment

    Intel® Quartus® Prime Pro Edition
    JESD204B Intel® FPGA IP
BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description

The JESD204C Intel® FPGA IP in Intel® Quartus® Prime Pro version 19.4 shares the synchronizer from the Transceiver (PHY).

The JESD204C Intel® FPGA IP in base only mode does not contain the Transceiver (PHY), which results in IP generation failure due to missing files for this mode. 

Resolution

This problem is fixed in Intel® Quartus® Prime Pro Edition software version 20.1 and above. 

Related Products

This article applies to 3 products

Intel Agilex® 7 FPGAs and SoC FPGAs F-Series
Intel® Stratix® 10 MX FPGA
Intel® Stratix® 10 TX FPGA

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