Article ID: 000076490 Content Type: Troubleshooting Last Reviewed: 03/23/2022

Why does my Intel® FPGA P-Tile Avalon® memory mapped IP for PCI Express* End Point show lower read performance with the Intel® Quartus® Prime Pro version 19.3?

Environment

    Intel® Quartus® Prime Pro Edition
    Avalon-MM Intel® Stratix® 10 Hard IP for PCI Express
    PCI Express
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Description

The Intel® FPGA P-Tile Avalon® memory mapped IP for PCI Express* supports up to 64 outstanding requests with a Max Read request size of 512 Bytes with the Intel® Quartus® Prime Pro version 19.3. If the round trip latency (Time from Memory Read to Completion) is greater than 1.5 us, the number of outstanding requests may not be enough to saturate the Read throughput. 

Resolution

This problem is fixed starting with the Intel® Quartus® Prime Pro Edition Software version 21.3.

Related Products

This article applies to 2 products

Intel Agilex® 7 FPGAs and SoC FPGAs F-Series
Intel® Stratix® 10 DX FPGA

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