Article ID: 000076490 Content Type: Troubleshooting Last Reviewed: 05/05/2021

Why does my Intel® FPGA P-Tile Avalon® memory mapped IP for PCI Express* End Point show lower read performance with the Intel® Quartus® Prime Pro version 19.3?

Environment

  • Intel® Agilex™ F-Series FPGAs and SoC FPGAs
  • Intel® Stratix® 10 DX FPGA
  • Intel® Quartus® Prime Pro Edition
  • Avalon-MM Intel® Stratix® 10 Hard IP for PCI Express
  • PCI Express
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    The Intel® FPGA P-Tile Avalon® memory mapped IP for PCI Express* supports up to 64 outstanding requests with a Max Read request size of 512 Bytes with the Intel® Quartus® Prime Pro version 19.3. If the round trip latency (Time from Memory Read to Completion) is greater than 1.5 us, the number of outstanding requests may not be enough to saturate the Read throughput. 

    Resolution

    This problem is scheduled to be fixed in a future release of the Intel® Quartus® Prime Pro Edition software.

    Disclaimer

    1

    All postings and use of the content on this site are subject to Intel.com Terms of Use.