Article ID: 000076486 Content Type: Troubleshooting Last Reviewed: 10/23/2020

When using the Intel® Arria® 10 PCIe* Hard IP in CvP or Autonomous mode, can the PLLs or transceivers be recalibrated in user mode if the reference clock is not stable during power up.

Environment

  • Intel® Arria® 10 FPGAs and SoC FPGAs
  • Intel® Arria® 10 GX FPGA
  • Intel® Arria® 10 GT FPGA
  • Intel® Arria® 10 SX SoC FPGA
  • Intel® Cyclone® 10 GX FPGA
  • Intel® Quartus® Prime Pro Edition
  • Intel® Arria® 10 Cyclone® 10 Hard IP for PCI Express
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    Description

    When using the Intel® Arria® 10 PCIe* Hard IP in CvP or Autonomous mode, it is a requirement that the PCIe* reference clock is either stable from power up or stable from the point it is enabled prior to the release of the nPERST#.

    The PCIe* reference clock must not be unstable during the PCIe Hard IP PLL or transceiver calibration phase.
     

    Resolution

    It is not possible to instigate a user mode re-calibration of the transceivers if this happens.

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