Article ID: 000076454 Content Type: Troubleshooting Last Reviewed: 04/22/2021

What are the calibration sequences for the Intel® Stratix® 10 EMIF IP?

Environment

  • Intel® Quartus® Prime Pro Edition
  • External Memory Interfaces Intel® Stratix® 10 FPGA IP
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    After FPGA device configuration, below are the calibration sequences for the Intel® Stratix® 10 EMIF IP.

    For the non-HPS EMIF IP, the sequences are on-chip termination (OCT) calibration, I/O PLL calibration, and then the EMIF calibration.

    For the HPS EMIF IP, the OCT / PLL / EMIF calibration sequences are done in the HPS-first phase and then the rest of the FPGA is done in the FPGA-first mode.

    The I/O PLL calibration for non-EMIF PLLs is also split between before user-mode entry and after user-mode entry depending on the configuration of the PLL itself.  If the PLL uses internal compensation modes, it is calibrated before user-mode entry.  If it uses core compensation modes, it is calibrated after user-mode entry.  All of this happens before EMIF calibration though, which is done entirely in user-mode.

    Related Products

    This article applies to 1 products

    Intel® Stratix® 10 FPGAs and SoC FPGAs