Article ID: 000076430 Content Type: Troubleshooting Last Reviewed: 08/04/2023

Rule C103: Gated clock does not feed at least a pre-defined number of clock ports to effectively save power

Environment

    Quartus® II Software
BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description

You may see the following warning when running the Design Assistant tool in Quartus II software on your compiled HPS design.

Rule C103: Gated clock does not feed at least a pre-defined number of clock ports to effectively save power ; <hierarchy>:altdq_dqs2_inst|dqsbusout

 

Resolution

This warning is expected and can be safely ignored.

Related Products

This article applies to 6 products

Arria® V SX SoC FPGA
Arria® V GT FPGA
Cyclone® V SX SoC FPGA
Cyclone® V ST SoC FPGA
Cyclone® V SE SoC FPGA
Arria® V ST SoC FPGA

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