Article ID: 000076403 Content Type: Product Information & Documentation Last Reviewed: 08/15/2014

How do I stitch multiple MIF files generated by the Quartus II software into a single MIF file, for fPLL reconfiguration in Stratix V, Arria V and Cyclone V devices?

Environment

BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description

You can stitch multiple Memory Initialization Files (MIF) generated by Quartus® II software into a single MIF file for fPLL reconfiguration in Stratix®  V, Arria®  V and Cyclone®  V devices using the script provided in the link below:

merge_mif.tcl

To use the script, follow the steps below:

1. Place the tcl file and the MIF files in the same folder.

2. Source the merge_mif.tcl in tcl console.

3. Type the following command to stich 2 mif files (e.g A.mif and B.mif) into output.mif.

Command : stitch A.mif  B.mif [output.mif]

Note : If you do not specify the optional [output.mif] paramater, it defaults to merged.mif.

4. In merged.mif, the content of B.mif comes after A.mif.

5. Repeat step 3 if you want to merge another MIF file (e.g C.mif) to merged.mif . You can stitch multiple MIF files together as long as the depth of the merged file does not exceed 512.

 

Refer to AN661 : Implementing Fractional PLL Reconfiguration with Altera PLL and Altera PLL Reconfig Megafunctions (PDF)  for more information on performing PLL reconfiguration via MIF streaming.

 

Related Products

This article applies to 17 products

Cyclone® V ST SoC FPGA
Arria® V ST SoC FPGA
Arria® V GX FPGA
Arria® V FPGAs and SoC FPGAs
Arria® V GT FPGA
Arria® V SX SoC FPGA
Cyclone® V FPGAs and SoC FPGAs
Cyclone® V E FPGA
Stratix® V E FPGA
Cyclone® V SE SoC FPGA
Stratix® V FPGAs
Cyclone® V GT FPGA
Stratix® V GX FPGA
Cyclone® V GX FPGA
Stratix® V GT FPGA
Stratix® V GS FPGA
Arria® V GZ FPGA

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