Article ID: 000076354 Content Type: Troubleshooting Last Reviewed: 12/29/2022

Does the Viterbi IP support 1/3 mother code with high puncture rate?

Environment

    Intel® Quartus® Prime Pro Edition
    Viterbi Intel® FPGA IP
BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description

Yes, the Viterbi IP supports 1/3 mother code with a high puncture rate (e.g., 70/72 code rate). However, because of the high error rate, short message frame, tailbiting termination, and if the traceback (TB) is not long enough, the IP may not correctly predict the trellis starting/ending point, and the IP eventually decodes the frame incorrectly.

Resolution

Assuming the traceback (TB) is 105 bits, the message frame length is 70 bits, encoded using tailbiting termination, and the code rate is 70/72. In this case, the Viterbi decoder is very poor at correcting errors.  Therefore, each input frame must feed consecutively three times (two traceback lengths TB0 TB1), followed by a number of zeros (TB2). The first and second output frames may still contain errors because the IP cannot predict the trellis starting/ending point correctly, but with no error at the third output frame. Therefore, ignore the first and second output frames for this case.

Related Products

This article applies to 9 products

Arria® II GZ FPGA
Arria® V FPGAs and SoC FPGAs
Intel® Arria® 10 FPGAs and SoC FPGAs
Cyclone® IV FPGAs
Cyclone® V FPGAs and SoC FPGAs
Stratix® IV FPGAs
Intel® MAX® 10 FPGAs
Stratix® V FPGAs
Arria® II GX FPGA

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