Article ID: 000076332 Content Type: Troubleshooting Last Reviewed: 01/09/2019

Why does the interface 1 port simulate incorrectly when the abstract phy simulation model is used in the Intel® Arria® 10 DDR4 Ping Pong PHY IP?

Environment

  • Intel® Quartus® Prime Pro Edition
  • External Memory Interfaces Intel® Arria® 10 FPGA IP
    • BUILT IN - ARTICLE INTRO SECOND COMPONENT

    Critical Issue

    Description

    When using the Intel® Quartus® Prime software version 17.1.2 or earlier, you may see the interface 1 port simulate incorrectly when the Intel Arria® 10 DDR4 Ping Pong PHY IP is configured with both the Abstract phy for simulation option and the Write DBI option enabled.

    Note that the interface 0 port simulates correctly.

    Resolution

    This problem is fixed in the Intel® Quartus® Prime software version 18.0 or newer.

    Related Products

    This article applies to 1 products

    Intel® Arria® 10 FPGAs and SoC FPGAs

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