Article ID: 000076314 Content Type: Error Messages Last Reviewed: 10/21/2020

Error(14566): The Fitter cannot place x periphery component(s) due to conflicts with existing constraints (x IOPLL(s)).

Environment

  • Intel® Stratix® 10 FPGAs and SoC FPGAs
  • Intel® Cyclone® 10 GX FPGA
  • Intel® Arria® 10 FPGAs and SoC FPGAs
  • Intel® Quartus® Prime Pro Edition
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    Due to restriction of the Triple-Speed Ethernet Intel® FPGA IP with option "LVDS" as "Transceiver type", IOPLLs can't be merged.

    You may see this error in the Intel® Quartus® Prime software when you initiate multiple Triple-Speed Ethernet Intel® FPGA IP with option "LVDS" as "Transceiver type" in single I/O bank for the Intel® Arria® 10, Intel® Cyclone® 10 GX or Intel® Stratix® 10 L-Tile/H-Tile device.

    Resolution

    To avoid this error, follow the steps below:

    1, Generate the Triple-Speed Ethernet Intel® FPGA IP with option "None" as "Transceiver type".

    2, Generate the LVDS SERDES Intel® FPGA IP with multiple channels.

    3, Connect two IPs manually.

    This problem will not be fixed in a future version of the Intel® Quartus® Prime software.

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