Article ID: 000076312 Content Type: Troubleshooting Last Reviewed: 02/15/2023

Why does the Timing Analyzer report minimum period timing violation in the Intel® Arria® 10 Native Fixed Point DSP IP?

Environment

    Intel® Quartus® Prime Pro Edition
    Native Fixed Point DSP Intel® Arria® 10 FPGA IP
BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description

A minimum timing period violation may be seen if the DSP block is not fully registered.

 

 

Resolution

To work around this problem, enable the input, output, and pipeline register using the IP GUI to ensure timing is met when using the Intel® Arria® 10 Native Fixed Point DSP IP.

Related Products

This article applies to 1 products

Intel® Arria® 10 FPGAs and SoC FPGAs

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