Critical Issue
Due to a problem with the Avalon® -ST Intel® Stratix® 10 Hard IP for PCI Express and Avalon® -MM Intel® Stratix® 10 Hard IP for PCI Express in Intel® Quartus® Prime Pro Edition Software version 19.4, the Slot Clock Configuration bit (bit 12) in the PCI Express Link Status register is always set to 0. This problem can be seen in both simulation and hardware.
There is no workaround. This problem will be fixed in a future version of the Intel® Quartus® Prime Pro Edition Software.