Article ID: 000076251 Content Type: Troubleshooting Last Reviewed: 06/19/2020

Why is the Slot Clock Configuration bit setting of the Avalon® -ST Intel® Stratix® 10 Hard IP for PCI Express* and Avalon® -MM Intel® Stratix® 10 Hard IP for PCI Express* is always 0 regardless of the setting in the IP Catalog ?

Environment

  • Intel® Stratix® 10 GX FPGA
  • Intel® Stratix® 10 MX FPGA
  • Intel® Stratix® 10 TX FPGA
  • Intel® Stratix® 10 DX FPGA
  • Intel® Stratix® 10 SX SoC FPGA
  • Intel® Quartus® Prime Pro Edition
  • Avalon-MM Intel® Stratix® 10 Hard IP for PCI Express
  • Avalon-ST Intel® Stratix® 10 Hard IP for PCI Express
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT

    Critical Issue

    Description

    Due to a problem with the Avalon® -ST Intel® Stratix® 10 Hard IP for PCI Express* and Avalon® -MM Intel® Stratix® 10 Hard IP for PCI Express* in Intel® Quartus® Prime Pro Edition version 19.4, the Slot Clock Configuration bit (bit 12) in the PCI Express Link Status register is always set to 0. This problem can be seen in both simulation and hardware. 

    Resolution

    There is no workaround. This problem will be fixed in a future version of the Intel® Quartus® Prime Pro Edition software.

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