Article ID: 000076242 Content Type: Troubleshooting Last Reviewed: 03/16/2021

Why do I see the warning "Associated reset sinks not declared" when using the Intel® Arria® 10/Cyclone® 10 Hard IP for PCI* Express and "Enable dynamic reconfiguration of the PCIe* read-only registers" is enabled?

Environment

  • Intel® Arria® 10 SX SoC FPGA
  • Intel® Cyclone® 10 GX FPGA
  • Intel® Arria® 10 FPGAs and SoC FPGAs
  • Intel® Arria® 10 GT FPGA
  • Intel® Arria® 10 GX FPGA
  • Intel® Quartus® Prime Pro Edition
  • Intel® Arria® 10 Cyclone® 10 Hard IP for PCI Express
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    Critical Issue

    Description

    Due to a problem in the Intel® Arria® 10/Cyclone® 10 Hard IP for PCI* Express the error "Associated reset sinks not declared" will be seen when "Enable dynamic reconfiguration of the PCIe* read-only registers" is enabled.

    The "Associated reset sinks not declared" warning, is intended to detect possible reset loops. If asserting a reset input on the component drives the reset output high, then you need to set the associated reset sinks parameter. If there is no relationship between the resets you can set "none" as the value.

    This warning does not affect functionality.

    Resolution

    These warnings can be safely ignored as functionality is not impacted when using the Intel® Arria® 10/Cyclone® 10 Hard IP for PCI* Express.

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