Why does VCS* simulation fail for the example design testbench of the 25G Ethernet Intel® Stratix® 10 FPGA IP variant with PTP, RSFEC, and VHDL options chosen?

Due to a problem in the Intel® Quartus® Prime Pro Edition Software version 19.3 and earlier, the VCS* simulation of the example design’s testbench of the 25G Ethernet Intel® Stratix® 10 FPGA IP variant with PTP, RSFEC, and VHDL options chosen will fail in VCS with “Cross-module reference resolution error.”

To work around this problem perform the following steps:

        1.)   Navigate to the example design’s “example_testbench/” directory

        2.)   Open the “basic_avl_tb_top.sv” file

        3.)   Comment out line 40:

                 defparam singleport1588_s10gxt_inst.s10_top.alt_e25s10_0.SIM_SHORT_AM       = 1'b1;

         4.)   Recompile the simulation