Article ID: 000076240 Content Type: Troubleshooting Last Reviewed: 09/24/2019

Why does VCS* simulation fail for the example design testbench of the 25G Ethernet Intel® Stratix® 10 FPGA IP variant with PTP, RSFEC and VHDL options chosen?

Environment

  • Intel® Stratix® 10 FPGAs and SoC FPGAs
  • Intel® Quartus® Prime Pro Edition
  • 25G Ethernet Intel® FPGA IP
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT

    Critical Issue

    Description

    Due to a problem in the Intel® Quartus® Prime Pro software version 19.3 and earlier, the VCS* simulation of the example design’s testbench of the 25G Ethernet Intel® Stratix® 10 FPGA IP variant with PTP, RSFEC and VHDL options chosen will fail in VCS with “Cross-module reference resolution error”.

    Resolution

    To work around this problem perform the following steps:

            1.)   Navigate to the example design’s “example_testbench/” directory

            2.)   Open the “basic_avl_tb_top.sv” file

            3.)   Comment out line 40:

                     defparam singleport1588_s10gxt_inst.s10_top.alt_e25s10_0.SIM_SHORT_AM       = 1'b1;

             4.)   Recompile the simulation

     

    This problem is scheduled to be fixed in a future release of the Intel Quartus Prime Pro software.

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