Low Latency 40-100GbE IP Core User Guide Swaps Addresses of Statistics Module FCS and CRCERR Registers

The Low Latency 40-100GbE IP core user guide incorrectly identifies the addresses of eight statistics module registers.

Correct addresses of CNTR_TX_CRCERR registers are 0x806 and 0x807.

Correct addresses of CNTR_RX_CRCERR registers are 0x906 and 0x907.

Correct addresses of CNTR_TX_FCS registers are 0x804 and 0x805.

Correct addresses of CNTR_RX_FCS registers are 0x904 and 0x905.

However, the user guide lists them at each other’s addresses.

This issue has no workaround. You must access these registers at the correct addresses listed in this erratum and ignore the erroneous addresses listed in the user guide.

This issue is fixed in the 2014.08.18 version of the Low Latency 40- and 100-Gbps Ethernet MAC and PHY MegaCore Function User Guide.