Article ID: 000075988 Content Type: Troubleshooting Last Reviewed: 12/11/2012

Do I have to drive both ports of a differential a pin in gate level simulation netlists or do I need to provide a true differential input?

Environment

    Quartus® II Subscription Edition
    Simulation
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Description

If your top level design in the Quartus® II software instances Altera differential IO buffers or uses IP blocks with top level differential inputs ( p and n ports at the top level) your external logic must drive a true differential signal into the Quartus II generated netlist.

If an Altera Differential IO buffer model sees an unbalanced input it will drive X onto the output.

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Intel® Programmable Devices

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