Description
EXTEST is mandatory IEEE Std. 1149.1 Joint Test Action Group (JTAG) instruction. It tests the "external" traces of a device.
Resolution
The following steps provide a brief explanation of how the EXTEST testing works:
- The boundary scan register is connected between TDI and TDO and the device is placed in an “external” test mode
- Boundary-scan output cells (the source) drive a known logic high and low value onto the trace being tested.
- Boundary-scan input cells (the destinations) connected to this trace capture the value on this trace.
- If the expected values match, the trace is fine. If not, the trace is either open or shorted.
The high-impedance state of EXTEST is overridden by bus hold and weak pull-up resistor features.